The invention relates to a method and a semiconductor wafer configuration for producing an alignment mark for semiconductor wafers.
Integrated circuits (on semiconductor wafers) have a center position error of two structures lying one above the other (e.g., an interconnect above a contact hole) which is only permitted to amount to about a third of the minimum structure in order to be able to utilize the maximum possible packing density of the structures. The formation of structures on semiconductor wafers is usually effected with the aid of lithographic methods. Firstly, the structures are produced by a photomask in a thin radiation-sensitive film (usually an organic photoresist layer) on the semiconductor wafer. Then, they are transferred to the underlying semiconductor layer by special etching methods.
Accordingly, it is necessary to perform an accurate alignment of the exposure device for imaging the photomask on the resist layer (for accurately superimposing a new mask structure with a structure already present on the wafer). The alignment is generally performed using alignment marks, which are provided on the semiconductor wafer (and which can be used to ascertain position errors with regard to the location of corresponding marks on the photomask according to size and direction), in order to correct the position error through a relative movement between the mask and the wafer.
Depressions on the semiconductor wafer are generally used as alignment marks. The depressions are preferably formed in the intermediate region, between the individual integrated circuits on the semiconductor wafer. The depressions are usually detected by light-optical alignment mark identification methods (e.g., xe2x80x9cedge contrastxe2x80x9d method).
The alignment marks are preferably formed in the context of the formation of a structure plane for fabricating integrated circuits on the semiconductor wafer. The alignment marks are defined on a photoresist layer (using lithography technology), and then are transferred to the underlying semiconductor wafer with etching. It is generally necessary (for uncovering the etching mark) to etch through a layer sequence of different dielectric layers that are stacked one above the other. Further, it is particularly true when the alignment marks serve for the alignment of masks used (in the downstream part of the fabrication process of the electrical circuits) for making contact with and connecting the individual components of the integrated circuit.
However, the uncovering of a layer stack for the formation of the alignment marks gives rise to the problem that the layers separate from one another during subsequent fabrication processes (e.g., a chemical mechanical polishing or an etching operation). Accordingly, the form of the alignment marks and the alignment mark detection signal are altered undesirably. Furthermore, there exists the risk that constituent parts of the uncovered sidewall of the alignment marks may become detached during subsequent process steps (thereby, impairing the final filling of the alignment marks). Likewise, the filled layer can become detached from the sidewalls, and the alignment mark form can thus be altered undesirably.
FIG. 1A illustrates the problem of the detachment of the layer sequence in an alignment mark depression. The alignment mark depression 6 has been produced in the context of the fabrication of contact openings for connecting different metal planes. A layer sequence of three dielectric layers 1, 2, 3 (disposed above one another) has been etched through, and the alignment mark depression 6 is filled with a contact metal 5 (after the etching operation) together with the other contact holes.
Subsequently, a chemical mechanical polishing operation (CMP) is carried out for removing the contact metal 5 again from the surface of the dielectric layer sequence. However (during the polishing operation), there exists the risk (as shown at the location identified by reference symbol 4) that the topmost dielectric layer 3 may become detached from the intermediate dielectric layer 2. As shown in FIG. 1B, there exists another risk (during the cleaning step that is subsequently carried out) of the occurrence of an undesirable incipient etching of the intermediate dielectric 2 (at the location identified by reference symbol 7). It can result in an undesirable depression in the alignment mark sidewall. Consequently, the adhesion of the contact metal filling 5 to the sidewall is reduced to such an extent that parts of the metal filling in the alignment marks become detached during the CMP step.
It is an object of the invention to provide a method and a semiconductor wafer configuration for producing an alignment mark for semiconductor wafers, that overcome the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type. The present invention is distinguished by an improved alignment mark.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a method for fabricating an alignment mark on a semiconductor wafer. In the method, an alignment mark region surrounded by a metal frame is formed on the semiconductor wafer, and at least one dielectric layer is deposited for completely burying the metal frame with the alignment mark region.
Next, the alignment mark area is defined in the alignment mark region with a photolithography process in such a way that the boundary of the alignment mark area lies at a uniform distance within the boundary of the alignment mark region, defined by the metal frames. Then, the dielectric layer is uncovered in the alignment mark region by anisotropic etching in such a way that the alignment mark opening extends at least as far as the level of the metal frame.
Providing a uniform metal frame around the alignment mark depression helps avoid any detachment of the dielectric material at the sidewall of the alignment mark. The alignment mark formed, according to the invention, with a peripheral metal frame also retains its form in subsequent process steps. This ensures that the alignment mark contrast remains the same, thereby further ensuring reliable alignment mark identification.
In accordance with another feature of the invention, the peripheral metal frame is preferably fabricated in the context of damascene technology. A dielectric layer is deposited on the semiconductor wafer, and the metal frame structure is defined with a lithography process. Afterward, the metal frame structure is uncovered by anisotropically etching the dielectric layer and filling it with a metal layer. The metal layer is then removed as far as the surface of the dielectric layer, thereby producing a metal frame. In accordance with this embodiment, the alignment mark can be fabricated without an increased outlay, in the context of the standard damascene technique (that is customarily used to produce contacts between metal planes).
In accordance with a further feature of the invention, the formation of the metal frame in the alignment mark region is performed by applying a metal layer, defining the alignment mark region and anisotropically etching the metal layer for uncovering the alignment mark region. This simple technique makes it possible to produce the alignment mark frame for an improved protection of the alignment mark sidewall, in the context of the conventional formation of an interconnect plane.
In accordance with an added feature of the invention, the metal frame has several interleaved frame structures. This helps in optimally coordinating the metal frame structure with the uncovered layer sequence of the alignment mark depression. The reliable prevention of detachment processes between the different layers (or of undercutting in the alignment mark wall) is thereby achieved.
In accordance with an additional feature of the invention, the alignment mark region and the alignment mark area are rectangular.
With the objects of the invention in view, there is also provided a semiconductor wafer configuration for producing an alignment mark. The semiconductor wafer configuration includes a semiconductor wafer, a dielectric layer formed with a depression having a sidewall, and disposed on the semiconductor wafer. The configuration further includes a metal frame disposed on the semiconductor wafer. The metal frame completely encloses the depression and is at a uniform distance from the sidewall of the depression. The depression extends at least as far as the level of the metal frame.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method and a semiconductor wafer configuration for producing an alignment mark for semiconductor wafers, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.